Top all-time · #2506
Alastair Reid
Personal blog · alastairreid.github.io · on HN as adreidsystemsprogramming
Alastair Reid's personal blog at alastairreid.github.io covers systems and programming. Since 2016, 33 different Hacker News readers have linked it 57 times, most often “Rust Verification Tools”. The last post was in 2024, but the archive is still widely read.
Researcher at Intel
Most-linked posts?
- Rust Verification Tools7 people · 8 mentions · first linked 2020-05-08
- The ARM Scalable Vector Extension [pdf]4 people · 4 mentions · first linked 2017-05-11
- /ARM-v8a-xml-release/3 people · 3 mentions · first linked 2019-04-23
- Automatic Rust verification tools (2021)3 people · 3 mentions · first linked 2021-06-03
- Rust Design-for-Testability: A Survey3 people · 3 mentions · first linked 2020-10-30
- ARM Releases Machine Readable Architecture Specification3 people · 3 mentions · first linked 2017-04-20
- Machine Readable Specifications at Scale2 people · 3 mentions · first linked 2022-01-26
- What can you do with an ISA specification?2 people · 3 mentions · first linked 2021-11-25
- Dissecting ARM's Machine Readable Specification2 people · 2 mentions · first linked 2017-05-01
- Who Guards the Guards? Formal Validation of the ARM v8-M Architecture Spec'n [pdf]2 people · 2 mentions · first linked 2017-08-24
What Hacker News says?
"In the wild" one hardly ever has to write unsafe Rust data structures and algorithms. > If the motivation to bring a new tool is pronounced as "let's make it safe", why should we allow the argument to fallback into the "unsafe Rust" territory? Because going from 0% of code proven safe by the compiler to 99% is very valuable. Verifying the remaining code is desirable but not as valuable as what Rust already provides…
Comment linking /rust-verification-tools/
on “Supporting Linux kernel development in Rust”Submitted Verifying ARM processors against the official ARM specification as a story · 219 points
HN discussionAh, they indeed have a shorter spec, but it's at 2611 pages now https://static.docs.arm.com/ddi0596/d/ISA_A64_xml_v85A-2019-... It's actually a document generated from machine-readable XML files https://alastairreid.github.io/ARM-v8a-xml-release/
Comment linking /ARM-v8a-xml-release/
on “IBM Open-Sources Power Chip Instruction Set”Submitted ARM Releases Machine Readable Architecture Specification as a story · 167 points
HN discussionRust makes it easy to write code that's very expressive (dynamic memory allocation etc) and has strong safety properties. Certainly easier than having to verify with SPARK or Frama-C. Rust's type system, especially traits and affine types, lets you encode a lot of important properties (e.g. typestates). Rust does need tools to verify Rust code correctness and especially to verify unsafe Rust code. There is a lot of…
Comment linking /rust-verification-tools/
on “Linux kernel in-tree Rust support”Submitted How to improve the RISC-V specification as a story · 162 points
HN discussionHere's a 2020 overview of Rust verification tools https://alastairreid.github.io/rust-verification-tools/ - it says > Auto-active verification tools > While automatic tools focus on things not going wrong, auto-active verification tools help you verify some key properties of your code: data structure invariants, the results of functions, etc. The price that you pay for this extra power is that you may have to assist…
Comment linking /rust-verification-tools/
on “Prusti: Static Analyzer for Rust”Submitted Rust testing or verifying: Why not both? as a story · 143 points
HN discussion> I've never known any of XML's features to help with actually solving a business problem. Arm are publishing their full ISA processor specifications in XML, so it is 100% machine readable, see [1] for the actual specification and [2, 3] for why you want a machine readable ISA spec in the first place. Arm has been really ahead with this, and all the other processor manufacturer are playing catchup. I'm not saying th…
Comment linking /uses-for-isa-specs/
on “IETF should keep XMPP as IM standard, instead of Matrix”Submitted Formal Verification Tool Competitions as a story · 67 points
HN discussionThere has been a steady industry of people retyping the manuals of all the major architectures for use in formal verification. At PLDI last year, there was even a paper where a team used synthesis techniques to automatically generate an instruction spec for x86 by generating tests for processors and using the answers to refine their current guess. And within ARM, there were lots of people transcribing bits of the AR…
Comment linking /papers/srepls4-trustworthy.pdf
on “ARM Releases Machine Readable Architecture Specification”Submitted What can you do with an ISA specification? as a story · 51 points
HN discussionThis has been available for arm for some years. Here is a blog post I wrote at around the time it was released. The easiest bits to use would be the instruction formats and the register fields https://alastairreid.github.io/dissecting-ARM-MRA/
Comment linking /dissecting-ARM-MRA/
on “How to improve the RISC-V specification”Submitted Managing risks in research as a story · 44 points
HN discussionNot really. The 3439 page Intel® 64 and IA-32 Architectures Software Developer’s Manual is a specification . It just isn't a formal specification suitable for use in proving properties of programs. ARM on the other hand, released a machine readable architecture specification for ARMv8 but that architecture isn't as old or as large as x86_64. Nor is Intel/AMD in the business of selling architecture licenses where hav…
Comment linking /ARM-v8a-xml-release/
on “A Complete Formal Semantics of x86-64 User-Level Instruction Set Architecture”Submitted Are natural language specifications useful? as a story · 39 points
HN discussion> formal methods based on proof assistants never took off A few examples of large scale industrial projects using formal assistants: seL4: A proven correct commercial OS used in billions of mobile devices. CompCert: A proven correct C compiler used by Airbus for avionics software. ARM: End-to-end verification of CPUs ( https://alastairreid.github.io/papers/CAV_16 ). There are many more.
Comment linking /papers/CAV_16
on “Formalizing Text Editors in Coq”Submitted Machine Readable Specifications at Scale as a story · 37 points
HN discussionhere we go: https://blog.rust-embedded.org/newsletter-31/ autmotive (plastered with 1bn+$ companies) is actively exploring rust for functional safety, via AUTOSAR, and adacore and ferrous systems partner up for rust in ada-affine industries. rust has this lovely habit of validating their compiler updates with their full collection of libraries, that's one step ahead of the validation contribution of SUSE, redhat, de…
Comment linking /automatic-rust-verification-tools-2021/
on “Learn Effective C++ for Embedded Code”Submitted The ARM Scalable Vector Extension [pdf] as a story · 13 points
HN discussionI wonder what Charlie Demerjian is going to say about this. It is an awful lot of registers for a feature that few programs may use. There's the risk that bfloat16 is a fad and five years from now it is used hardly at all. At best it is for a full stack perception-and-synthesis feature about as good as https://en.wikipedia.org/wiki/Intel_Quick_Sync_Video Most of all it drives me nuts that Intel is going down the fix…
Comment linking /papers/sve-ieee-micro-2017.pdf
on “The x86 Advanced Matrix Extension”Submitted Industrial Verification of ARM Processors (2016) as a story · 11 points
HN discussion> I can only hope that ARM has learned from Intel's mistakes and the situation is better with their CPUs. How can we hope for bug-free software when even ISA semantics aren't clear? ARM's research division has spent a great deal of time on this topic. This is a good introduction and describes where they were at in 2018: https://alastairreid.github.io/talks/formalizing-arm-specs-A...
Comment linking /talks/formalizing-arm-specs-ACSD-2018-06-15.pdf
on “Stratified Synthesis: Automatically Learning the x86-64 Instruction Set (2016) [pdf]”Submitted ARM Releases Machine Readable Architecture Specification as a story · 10 points
HN discussionTLA+ operates at a different level both conceptually and in the SDLC than programming languages like Dafny or Rust. TLA+ is a design language rather than an implementation language and this permeates a lot of its foundations. FWIW you can already use Dafny to write individual modules in real-world programs (it compiles to .NET and therefore interoperates with e.g. C#), although there are still some rough edges given…
Comment linking /rust-verification-tools/
on “Dafny: Verification-Aware Programming Language”Submitted ARM Releases Machine Readable Architecture Specification as a story · 8 points
HN discussion> What worries me is that when it comes to safety, surely the chain is as strong as the weakest link? You declare one thing unsafe, and then suddenly, all bets are off. And maybe you don't even know that what you're doing is unsafe. Yes, you are correct. If some code or module contains a memory safety or data race bug, then the code which uses it could realize that bug in the form of a crash or race. This paper is n…
Comment linking /rust-verification-tools/
on “Is Rust Used Safely by Software Developers?”Submitted What can you do with an ISA specification? as a story · 4 points
HN discussionSail is not at the register-transfer level (RTL) [1]. Why? Because Sail does not offer abstractions for clocked digital circuits, which is what characterises the RTL. The most widely used DSL for the RTL is (System)Verilog [3]. Instead, Sail is a stand-alone DSL for the ISA (= instruction set architecture). The purpose of the ISA level is to talk about that a processor looks from the outside, to the programmer (most…
Comment linking /ARM-v8a-xml-release/
on “The Sail ISA specification language”Submitted Summarizing 12 months of reading papers as a story · 4 points
HN discussion
