Top all-time · #4381
Antmicro Blog
Company blog · antmicro.com/bloghardwareprogramming
Antmicro Blog is the company blog at antmicro.com, writing about hardware and programming. Since 2020, 17 different Hacker News readers have linked it 24 times, most often “VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA”. It is still writing: the last post was on 2026-10-27, and you can follow it by feed.
Most-linked posts?
- VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA3 people · 4 mentions · first linked 2020-05-21
- Running Rust Programs in SeL43 people · 3 mentions · first linked 2022-09-01
- Open source signal integrity analysis3 people · 3 mentions · first linked 2023-11-28
- Accelerating digital block design with Google's open source Mid-Level Synthesis2 people · 2 mentions · first linked 2023-09-18
What Hacker News says?
They sorely lack m2 for high throughput storage. A board with a m2 port costs an extra $300 and only exists since last year: https://antmicro.com/blog/2020/04/updated-jetson-nano-xavier... It should have been standard and by default from the beginning.
Comment linking /blog/2020/04/updated-jetson-nano-xavier-nx-baseboard-m2/
on “Neural networks emulate any guitar pedal for $120”Submitted VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA as a story · 174 points
HN discussionBaseboard management is switching to easily swapped modules for exactly this reason: https://antmicro.com/platforms/dc-scm-open-source-bmc-platfo... https://www.servethehome.com/the-ocp-dc-scm-hff-is-taking-ov...
Comment linking /platforms/dc-scm-open-source-bmc-platforms/
on “Supermicro server motherboards can be infected with unremovable malware”Submitted RPC DRAM support in open source DRAM controller as a story · 31 points
HN discussionPerhaps the more interesting page is: https://antmicro.com/blog/2022/08/running-rust-programs-in-s... More about Rust and the architecture. I know Renode of its RISC-V meetup presentations, can't say I was impressed favorably.
Comment linking /blog/2022/08/running-rust-programs-in-sel4/
on “Announcing KataOS and Sparrow”Submitted Zephyr FPGA Controller as a story · 25 points
HN discussionCheckout Surelog - https://antmicro.com/blog/2020/12/ibex-support-in-verilator-... and the more recent usage in https://github.com/siliconcompiler/siliconcompiler
Comment linking /blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
on “VRoom A high end RISC-V implementation”Submitted Running Rust Programs in SeL4 as a story · 4 points
HN discussionI have a Google Doc at < https://j.mp/softcpus-on-fpgas > which includes a bunch of information about what type of performance has been achieved on modern Xilinx FPGAs. You can generally do quite a bit of parallelism, see the quad-core LiteX+VexRISCV solution at < https://antmicro.com/blog/2020/05/multicore-vex-in-litex/ >.
Comment linking /blog/2020/05/multicore-vex-in-litex/
on “NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop”Submitted ZGlue Teams Up with Antmicro and Google in Open Chiplet Initiative as a story · 4 points
HN discussionCrypto-surplus hardware with same FPGA, https://www.hivelist.org/@apshamilton/acorn-215-xilinx-artix... & https://www.eevblog.com/forum/fpga/sqrl-acorn-as-an-interest... Artix-7 is supported by LiteX, an open-source toolchain based on reverse engineering of Xilinx bitstream, https://github.com/enjoy-digital/litex & https://antmicro.com/blog/2020/05/multicore-vex-in-litex/ These can be used for PCILeech DMA attacks/t…
Comment linking /blog/2020/05/multicore-vex-in-litex/
on “NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop”Submitted Accelerating digital block design with Google's open source Mid-Level Synthesis as a story · 3 points
HN discussionIt's taken many years of reverse engineering, but there's now an efficient OSS toolchain for the smaller Artix7 FPGA family, https://antmicro.com/blog/2020/05/multicore-vex-in-litex/
Comment linking /blog/2020/05/multicore-vex-in-litex/
on “AMD NPU and Xilinx Versal AI Engines Signal Processing in Radio Astronomy (2024) [pdf]”Submitted Running Rust programs in seL4 using the sel4-sys crate as a story · 3 points
HN discussionLooking through the DC-SCM specs [1], this thing is nuts . - 13 (*Thirteen*) separate I2C interfaces - 4 I3C interfaces (Update to I2C, still mostly proprietary) - 2 QSPI interfaces - 2 UART Interfaces - 2 USB-2.0 interfaces - PCIe 3.0 1x interface - PCIe 5.0 4x interface - JTAG to host system - Various simple control signals (power, ok, etc..) It's pretty goddamn future proof, though there's zero chance you could s…
Comment linking /blog/2021/07/dc-scm-open-hardware-for-fpga-bmc/
on “OpenPOWER Foundation Demoes the LibreBMC Power-Based Open-Source BMC”Submitted Open source RDIMM DDR5 Tester for Rowhammer memory vulnerability research (2023) as a story · 2 points
HN discussionThe team at Antmicro put together this pretty cool visualisation flow for this stuff using only open source tools -> https://antmicro.com/blog/2023/11/open-source-signal-integri...
Comment linking /blog/2023/11/open-source-signal-integrity-analysis/
on “Signal Reflections in Electronic Circuits”Submitted Deterministic Linux and Zephyr/micro-ROS testing in OSS Renode (2022) as a story · 1 points
HN discussionhttps://antmicro.com/blog/2022/01/fomu-keystroke-injector/
Comment linking /blog/2022/01/fomu-keystroke-injector/
on “Tomu – A family of devices which fit inside your USB port”Submitted Open source signal integrity analysis as a story · 1 points
HN discussionSubmitted High-frequency hardware design with open source signal integrity analysis as a story · 1 points
HN discussionSubmitted Open Source FPGA Design for SDI-MIPI Video Converter as a story · 1 points
HN discussionSubmitted Accelerating digital block design with Google’s open source XLS toolchain as a story · 1 points
HN discussionSubmitted Open Hardware Portal: opening the hardware design process with KiCad and Blender as a story · 1 points
HN discussion
