Top all-time · #4812
Colin Riley
Personal blog · labs.domipheus.com/bloghardwareprogramming
Colin Riley writes Domipheus Labs, a personal blog at labs.domipheus.com about hardware and programming. Since 2015, 16 different Hacker News readers have linked it 24 times, most often “Designing a CPU in VHDL, Part 1: Rationale, Tools, Method”. It is still writing: the last post was on 2025-06-29, and you can follow it by feed.
Too few sampled comments (7) to say how often HN recommends it.?
Why HN links it
HN readers link Colin Riley's blog for its FPGA and CPU design series, especially the VHDL CPU series that moves to RISC-V, and for Raspberry Pi PCI Express experiments.
Summarised by Claude from a sample of 7 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Most-linked posts?
- Designing a CPU in VHDL, Part 1: Rationale, Tools, Method4 people · 5 mentions · first linked 2015-06-19
- Raspberry Pi 4 PCI Express: It Works USB3, SATA GPUs?4 people · 4 mentions · first linked 2019-09-02
- Designing a CPU in VHDL2 people · 2 mentions · first linked 2018-03-09
What Hacker News says?
And here’s the link without the twitter wrapping: http://labs.domipheus.com/blog/raspberry-pi-4-pci-express-it...
Comment linking /blog/raspberry-pi-4-pci-express-it-actually-works-usb-sata-gpu/
on “Apple announces it will switch to its own processors for future Macs”Submitted Teensy Z80 Part 1 – Intro, Memory, Serial I/O and Display as a story · 96 points
HN discussionThere's at least one reported case of a PCIe multiplier card working with the Pi4: http://labs.domipheus.com/blog/raspberry-pi-4-pci-express-it...
Comment linking /blog/raspberry-pi-4-pci-express-it-actually-works-usb-sata-gpu/
on “WiFi 6 gets 1.34 Gbps on the Raspberry Pi CM4”Submitted Designing a CPU in VHDL, Part 1: Rationale, Tools, Method as a story · 88 points
HN discussionI wanted to post the same link! Additionally, there is (or was, it's offline but we still have the archived site) the HamsterWorks wiki: https://web.archive.org/web/20191020150416/http://www.hamste... Additionally, this guy completely made a CPU in VHDL. Later on in the series he adds HDMI support, implements the RISC-V ISA so that he can use GCC to compile programs for his CPU: http://labs.domipheus.com/blog/design…
Comment linking /blog/designing-a-cpu-in-vhdl-part-1-rationale-tools-method/
on “FPGA Developer Tutorials”Submitted Designing a RISC-V CPU in VHDL: Arty S7 RPU SoC as a story · 80 points
HN discussionAlas, this is a surprisingly hard question to answer, at least for FPGA design. Here are a few sites that helped me learn: * https://www.fpga4fun.com * http://fpgacpu.ca * https://www.nandland.com/verilog/tutorials/index.html * https://1bitsquared.com/pages/chat (Discord) And a few interesting blogs: * https://blackmesalabs.wordpress.com/ * https://tomverbeure.github.io * http://labs.domipheus.com/blog/ None of the…
Comment linking /blog/
on “Exploring FPGA Graphics (2020)”Submitted Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching as a story · 75 points
HN discussionSome guy started a series some weeks ago on designing a CPU for an FPGA: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-... For those interested in a more complex processor, RISC-V seems to be a processor on par with ARM in terms of features: http://riscv.org/
Comment linking /blog/designing-a-cpu-in-vhdl-part-1-rationale-tools-method/
on “Create Your Own CPU on an FPGA”Submitted Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing as a story · 51 points
HN discussionWould anyone familiar with the various qualities of FPGA boards care to weigh in on how to pick a good development board for this project? I personally know nothing about FPGA specs. Additionally, the first blog post in this series can be found at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...
Comment linking /blog/designing-a-cpu-in-vhdl-part-1-rationale-tools-method/
on “Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching”Submitted Teensy Z80 Part 2 – Mode 2 Interrupts, Timer as a story · 33 points
HN discussionThis series is also amazing: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-... In the end he switches to RISC-V as well
Comment linking /blog/designing-a-cpu-in-vhdl-part-1-rationale-tools-method/
on “Designing a RISC-V CPU, Part 2: Successfully executing (some) instructions”Submitted Designing a CPU in VHDL as a story · 5 points
HN discussionSubmitted Raspberry Pi 4 PCI Express: It Works USB3, SATA GPUs? as a story · 4 points
HN discussionSubmitted Designing a CPU in VHDL: VRAM and HDMI Output as a story · 4 points
HN discussionSubmitted Raspberry Pi 4 PCI Express (2019) as a story · 3 points
HN discussionSubmitted Teensy Z80 Computer – Part 4 – VRAM explained, display modes, simple shell as a story · 3 points
HN discussionSubmitted Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit as a story · 2 points
HN discussionSubmitted Designing a RISC-V CPU in VHDL 17: DDR3 Memory Controller, Clock Domain Crossing as a story · 2 points
HN discussionSubmitted TPU/RPU Series (Make CPU from FPGA) as a story · 2 points
HN discussionSubmitted Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM as a story · 2 points
HN discussionSubmitted Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality as a story · 1 points
HN discussionSubmitted Teensy Z80 Part 3 – File System, SD Card, VRAM? as a story · 1 points
HN discussion