Top all-time · #2429
dougallj
Personal blog · dougallj.wordpress.comsystemssecurityhardware
dougallj is a personal blog at dougallj.wordpress.com about systems, security and hardware. Since 2016, 31 different Hacker News readers have linked it 38 times, most often “Why is Rosetta 2 fast?”. The last post was in 2022, but the archive is still widely read.
Too few sampled comments (16) to say how often HN recommends it.?
Why HN links it
HN readers link this blog for low-level CPU and emulation writing, especially the Rosetta 2 analysis of x86-to-ARM translation and Apple Silicon flag handling. Other linked posts cover SIMD and CRC32 performance and emulator exploits.
Summarised by Claude from a sample of 16 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Most-linked posts?
- Why is Rosetta 2 fast?11 people · 12 mentions · first linked 2022-11-09
- Bitwise conversion of doubles using only floating point multiply and divide4 people · 4 mentions · first linked 2020-05-10
- Exploiting Dolphin – Part 14 people · 4 mentions · first linked 2016-11-14
- Faster CRC32 on the Apple M13 people · 3 mentions · first linked 2022-05-22
- Faster zlib/DEFLATE decompression on the Apple M1 (and x86)2 people · 3 mentions · first linked 2022-08-20
- Apple M1: Load and Store Queue Measurements – Dougallj2 people · 3 mentions · first linked 2021-04-08
- Bit-twiddling: optimising AArch64 logical immediate encoding and decoding2 people · 2 mentions · first linked 2021-10-30
- Bit-twiddling abstract addition with unknown bits (2020)2 people · 2 mentions · first linked 2020-01-13
What Hacker News says?
M1 has CRC32 acceleration intrinsics. https://dougallj.wordpress.com/2022/05/22/faster-crc32-on-th... https://github.com/corsix/fast-crc32?tab=readme-ov-file#appl...
Comment linking /2022/05/22/faster-crc32-on-the-apple-m1/
on “How Postgres stores data on disk – this one's a page turner”Submitted Why is Rosetta 2 fast? as a story · 650 points
HN discussionIn my experience the M1 does have competitive SIMD performance? https://dougallj.wordpress.com/2022/04/01/converting-integer... https://dougallj.wordpress.com/2022/05/22/faster-crc32-on-th... https://lemire.me/blog/2020/12/13/arm-macbook-vs-intel-macbo... (I later optimised the slower benchmark in that post: https://github.com/simdjson/simdjson/pull/1708 ) Obviously the GPU will be better, but at one point I compare…
Comment linking /2022/05/22/faster-crc32-on-the-apple-m1/
on “Linux M1 GPU driver passes 99% of the dEQP-GLES2 compliance tests”Submitted Faster CRC32 on the Apple M1 as a story · 343 points
HN discussionI found this blog post reverse engineering Rosetta 2 translated code: https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f...
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “Rosetta 2 creator leaves Apple to work on Lean full-time”Submitted Why is Apple Rosetta 2 fast? (2022) as a story · 177 points
HN discussion> I believe Rosetta 2 also has a JIT mode It does have JIT translation (not a JIT "mode" though, as it always use AOT translation, only relying on JIT translation at runtime for the parts that need it) > which is a bit more like conventional emulators Not at all†, Rosetta 2 does the same†† translation step on dynamic Intel code, whose arm64 output can be reused afterwards > But it's used infrequently, eg when dealin…
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “Factorio runs on Apple Silicon”Submitted Faster zlib/DEFLATE decompression on the Apple M1 (and x86) as a story · 170 points
HN discussionThere was just an article about exploits in Dolphin published yesterday that I found pretty interesting: https://dougallj.wordpress.com/2016/11/13/exploiting-dolphin... I agree this will probably catch on as a popular new vector, especially given the popularity of emulators on mobile devices.
Comment linking /2016/11/13/exploiting-dolphin-part-1/
on “Compromising a Linux desktop using 6502 opcodes on the NES”Submitted Parallelising Huffman decoding and x86 disassembly by synchronising prefix codes as a story · 73 points
HN discussionhttps://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f... > Apple M1 has an undocumented extension that, when enabled, ensures instructions like ADDS, SUBS and CMP compute PF and AF and store them as bits 26 and 27 of NZCV respectively, providing accurate emulation with no performance penalty.
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “FEX-emu – Run x86 applications on ARM64 Linux devices”Submitted Bitwise conversion of doubles using only floating point multiply and divide as a story · 69 points
HN discussionThe flags get saved and restored on task switches and interrupts. I would think deciding whether those bits actually get used across that is infeasible, but yet, https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f... says: “This almost entirely prevents inter-instruction optimisations. There are two known exceptions. The first is an “unused-flags” optimisation, which avoids calculating x86 flags value if th…
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “A secret Apple Silicon extension to accommodate an Intel 8080 artifact”Submitted Bit-twiddling abstract addition with unknown bits (2020) as a story · 67 points
HN discussionApple Arm CPUs have some special tricks to make x86 sogtware emulation faster. https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f...
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “What happened to Transmeta, the last big dotcom IPO”Submitted Reading bits with zero refill latency as a story · 55 points
HN discussionThis post was very helpful when I tried to figure it out: https://dougallj.wordpress.com/2021/10/30/bit-twiddling-opti...
Comment linking /2021/10/30/bit-twiddling-optimising-aarch64-logical-immediate-encoding-and-decoding/
on “Machine Code Isn't Scary”Submitted Apple M1: Load and Store Queue Measurements as a story · 6 points
HN discussionBesides TSO there are a bunch of ARM extensions designed to match x86 behavior. https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f... I'm curious whether Oryon and X925 implement these instructions and whether other emulators like FEX use them.
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “Intel and AMD form advisory group to reshape x86 ISA”Submitted Apple M1: Load and Store Queue Measurements – Dougallj as a story · 6 points
HN discussionSee “flag-manipulation” at https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f...
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “Executing ARM Jazelle (JVM Bytecode) on the Wii's Starlet”Submitted Bitwise conversion of doubles using floating-point multiplication and addition as a story · 5 points
HN discussionSomewhat related: https://dougallj.wordpress.com/2020/05/10/bitwise-conversion... That implements conversion from an IEEE-754 double to a pair of two such doubles whose values are integers of the low and high 32 bits of the bitwise representation of the argument double, implemented only with double add/sub/mul.
Comment linking /2020/05/10/bitwise-conversion-of-doubles-using-only-floating-point-multiplication-and-addition/
on “Subtraction Is Functionally Complete”Submitted Bit-Twiddling: Addition with Unknown Bits as a story · 4 points
HN discussionThe breakout engineering to exploit Dolphin has already happened, see for example: * https://dougallj.wordpress.com/2016/11/13/exploiting-dolphin... * https://gist.github.com/hthh/502ae16db55612f64d3966769a154c3... * https://github.com/dolphin-emu/dolphin/pull/4447
Comment linking /2016/11/13/exploiting-dolphin-part-1/
on “Dolphin Progress Release 2603”Submitted Faster zlib/DEFLATE decompression on ARM64 and x86 (2022) as a story · 3 points
HN discussion> There are only a handful of different instructions that account for 90% of all operations executed, and, near the top of that list are addition and subtraction. On ARM these can optionally set the four-bit NZCV register, whereas on x86 these always set six flag bits: CF, ZF, SF and OF (which correspond well-enough to NZCV), as well as PF (the parity flag) and AF (the adjust flag). > Emulating the last two in softw…
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “Windows GOG DOS Games on M-Series Macs”Submitted Converting integers to fixed-width strings faster with Neon SIMD on the Apple M1 as a story · 3 points
HN discussionThis is essentially what Apple did with Apple Silicon to make Rosetta fast: https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f... There’s a number of CPU features that make running translated x86 code much faster than it otherwise would be, like “Alternate Floating Point Mode” that happens to exactly match the x86’s floating point behavior.
Comment linking /2022/11/09/why-is-rosetta-2-fast/
on “Experts Weigh Impact of Intel-Arm Collaboration”Submitted Bit-twiddling: optimising AArch64 logical immediate encoding and decoding as a story · 3 points
HN discussion
