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FPGA CPU News
Personal blog · fpga.orghardwaresystems
FPGA CPU News is a personal blog at fpga.org about hardware and systems. Since 2016, 16 different Hacker News readers have linked it 19 times, most often “GRVI Phalanx joins The Kilocore Club”. The last post was in 2023, but the archive is still widely read.
Exploring Parallel Computer Architecture with FPGAs
Most-linked posts?
- GRVI Phalanx joins The Kilocore Club3 people · 3 mentions · first linked 2017-01-12
- Intel's 10nm Process Node, a 2.7x transistor density improvement2 people · 2 mentions · first linked 2017-03-30
- Introduction to Microscaling Formats (MX) Data2 people · 2 mentions · first linked 2023-11-28
- /grvi-phalanx/2 people · 2 mentions · first linked 2016-02-19
- The First Kilocore RISC-V RV64I with High Bandwidth Memory2 people · 2 mentions · first linked 2019-08-19
- /grvi-phalanx/2 people · 2 mentions · first linked 2024-05-30
What Hacker News says?
Jan Gray stuffed 400 RISC-V cores into a Xilinx Kintex UltraScale KU040 FPGA (and the KU115 is three times larger, not to mention the Virtex UltraScale range). http://fpga.org/grvi-phalanx/
Comment linking /grvi-phalanx/
on “Epiphany-V: A 1024-core 64-bit RISC processor”Submitted GRVI Phalanx joins The Kilocore Club as a story · 71 points
HN discussionAuthor: Thanks for taking the time to reply. I read the write-up with a LOT of interest, this is really amazing work, there's not a lot of good options for auto-routing with open-source PCB tools (i.e. KiCad). I have also used the other autorouter you mentioned for "low-complexity" boards in KiCad and it helped do the job but was painful. In my career I've also used the autorouter built into the "high-end" PCB tools…
Comment linking /grvi-phalanx/
on “OrthoRoute – GPU-accelerated autorouting for KiCad”Submitted Xilinx Project Everest: Everest: A New Adaptive Compute Acceleration Stack as a story · 4 points
HN discussionEven better than 88s: http://fpga.org/grvi-phalanx/
Comment linking /grvi-phalanx/
on “8088 microprocessor IP core fits in 308 LUTs, runs at 180MHz on a Kintex-7 FPGA”Submitted RISC-V at Scale: GRVI Phalanx Joins the Kilocore Club as a story · 4 points
HN discussionJan Gray is, I think, more-or-less the Godfather of this approach. I especially enjoyed his Circuit Cellar 3-part series where he describes and builds the xr16 -- a 16-bit machine whose instruction set is designed to well-match the LUT capabilities of an FPGA. I implemented it, and with the LCC C compiler, I was able to run plenty of code. Start here: https://github.com/BigEd/XSOC-xr16/blob/master/doc/xsoc-talk... w…
Comment linking /
on “ZipCPU – A small, lightweight, RISC soft core in Verilog”Submitted ‘Computing on Programmable Logic’ at Microsoft Research Faculty Summit 2016 as a story · 4 points
HN discussionSLM was at version 1.5 by 1988 and looking at chapter 5 suggests it had strong version number and external release management [1] [1]: https://fpga.org/wp-content/uploads/2023/09/SLM-1.5-Guides.p...
Comment linking /wp-content/uploads/2023/09/SLM-1.5-Guides.pdf
on “Microsoft Comic Chat is now open source”Submitted GRVI Phalanx Joins the Kilocore Club: RISC-V Scales Up as a story · 3 points
HN discussion> What does one do with such a cluster? They presented a short paper at FCCM '16: http://fpga.org/wp-content/uploads/2016/05/grvi_phalanx_fccm... Section VI lists possible applications.
Comment linking /wp-content/uploads/2016/05/grvi_phalanx_fccm2016.pdf
on “GRVI Phalanx joins The Kilocore Club”Submitted Intel's 10nm Process Node, a 2.7x transistor density improvement as a story · 2 points
HN discussionMore details here: https://fpga.org/grvi-phalanx/ Do note that these are simple cores intended to compete with GPGPU use.
Comment linking /grvi-phalanx/
on “Phalanx: A 1332-core RISC-V Processor Cluster Array (2019) [pdf]”Submitted GRVI Phalanx FPGA Update as a story · 2 points
HN discussionSubmitted Introduction to MicroScaling (MX) for AI Tensors as a story · 1 points
HN discussionSubmitted Introduction to Microscaling Formats (MX) Data as a story · 1 points
HN discussionSubmitted The First Kilocore RISC-V RV64I with High Bandwidth Memory as a story · 1 points
HN discussionSubmitted 2GRVI Phalanx at Hot Chips 31 (2019): The First Kilocore RISC-V RV64I with HBM2 as a story · 1 points
HN discussionSubmitted Intel’s New 10 Nm Process: The Wind in Our Sails as a story · 1 points
HN discussion
