Top all-time · #15132
Jan Decaluwe
Personal blog · jandecaluwe.com/bloghardwareprogramming
Jan Decaluwe's personal blog at jandecaluwe.com covers hardware and programming. Since 2014, 5 different Hacker News readers have linked it 9 times. No feed was found, so read it on the site itself.
Too few sampled comments (3) to say how often HN recommends it.?
Why HN links it
HN readers link Jan Decaluwe's hardware design writing, including his MyHDL work and essays on HDL design, such as arguing that HDLs are a simulation language. Commenters cite it in FPGA and HDL discussions.
Summarised by Claude from a sample of 3 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
What Hacker News says?
Wow 1997, but thanks for the link, it was a fun read. It'd be fun to hear from people in the industry what their experience has been on larger multi-people projects -- e.g. how long would it take to create an ASIC like http://www.jandecaluwe.com/hdldesign/digmac.html ?
Comment linking /hdldesign/digmac.html
on “Nyuzi: An experimental FPGA multicore GPGPU processor”Submitted Why do we need signal assignments? as a story · 4 points
HN discussionPSHDL is incredibly low-level & basic, afaik it doesn't even have functions & you can't define your own datatypes. I think it's a mistake to make a HDL language that aims to be 99% synthesize-able. I didn't write this but I do agree with it: http://www.jandecaluwe.com/blog/its-a-simulation-language.ht... I haven't looked a chisel yet (scala is my favorite software programming language though).
Comment linking /blog/its-a-simulation-language.html
on “Capturing a UART Design in MyHDL and Testing It in an FPGA”Submitted The Case for a Better HDL as a story · 3 points
HN discussionI think verilog (and mostly systemverilog) is beyond saving. Systemverilog has a spec bigger than c++ and it's full of broken, unused features or features that aren't compatible. Over the years they have added any feature that some HW engineer asked for resulting in a true kitchensink language. I don't think that there is a single simulator that implements the complete spec. (and on top of the regular language they…
Comment linking /blog/its-a-simulation-language.html
on “Capturing a UART Design in MyHDL and Testing It in an FPGA”Submitted A proposal to support the <mark> tag with Markdown as a story · 2 points
HN discussionSubmitted Thinking software at the RTL level as a story · 2 points
HN discussionSubmitted Chisel HDL: the latest instance of a flawed approach as a story · 1 points
HN discussionSubmitted Thinking software at the RTL level as a story · 1 points
HN discussion