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Lacking Rhoticity
Personal blog · lackingrhoticity.blogspot.comsystemshardware
Lacking Rhoticity is a personal blog at lackingrhoticity.blogspot.com about systems and hardware. Since 2008, 14 different Hacker News readers have linked it 15 times, most often “Observing interrupts from userland on x86”. The last post was in 2018, but the archive is still widely read.
Too few sampled comments (3) to say how often HN recommends it.?
Why HN links it
HN commenters link this blog for posts on cache associativity and Rowhammer, the DRAM bit-flip attack. The comments cite it as background and do not comment on the writing itself.
Summarised by Claude from a sample of 3 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Most-linked posts?
- Observing interrupts from userland on x862 people · 2 mentions · first linked 2018-01-09
- PassMark received offer to not release rowhammer test2 people · 2 mentions · first linked 2015-10-20
- How physical addresses map to rows and banks in DRAM (2015)2 people · 2 mentions · first linked 2016-10-29
What Hacker News says?
Ok, so you are talking about rowhammer. Let me try to put this in my own words. https://people.freebsd.org/~lstewart/articles/cpumemory.pdf DRAM is using hardware technology that is hard. Each dram bit can be addressed by ranks, banks, chips rows and columns. Depending on stuff, you typically read/load a whole cache line from DRAM. This is nice and easy. However, AFAIU there is delay needed in the chip after reading…
Comment linking /2015/04/l3-cache-mapping-on-sandy-bridge-cpus.html
on “Cache Associativity”Submitted Implementing fork() on the Mill CPU (2014) as a story · 93 points
HN discussionDRAM refresh occurs regularly and automatically, think of it as signal regeneration. But this does not correct bit flips, even on ECC memory. For ECC memory systems your idea is called ECC scrub . The idea is to trigger SBE correction before more bit flips occur, turning it into an unrecoverable or undetectable error. Usually it appears in BIOS as Patrol Scrub (continuously and slowly walk through all memory, slow e…
Comment linking /2015/05/how-physical-addresses-map-to-rows-and-banks.html
on “Defending against Rowhammer in the Linux kernel”Submitted CVS's problems resurface in Git as a story · 61 points
HN discussionA very similar approach, that attempts to refresh rows adjacent to the ones that are being repeatedly accessed is described here(disclosure: I am one of the authors of the paper): Paper: https://iss.oy.ne.ro/ANVIL.pdf Kernel Module Code: https://github.com/zaweke/rowhammer/tree/master/anvil It is tested on on an Intel SandyBridge CPU. For a full deployment, we would need to know which bits of the physical address ar…
Comment linking /2015/05/how-physical-addresses-map-to-rows-and-banks.html
on “Defending against Rowhammer in the Linux kernel”Submitted When printf debugging is a luxury (2010) as a story · 40 points
HN discussionSubmitted Python standard library in Native Client (AKA Python in the browser) as a story · 26 points
HN discussionSubmitted Python variable binding oddities as a story · 22 points
HN discussionSubmitted PassMark received offer to not release rowhammer test as a story · 4 points
HN discussionSubmitted Observing interrupts from userland on x86 as a story · 3 points
HN discussionSubmitted L3 Cache Mapping on Sandy Bridge CPUs as a story · 2 points
HN discussionSubmitted Using process descriptors instead of PIDs in FreeBSD's Capsicum as a story · 2 points
HN discussionSubmitted How physical addresses map to rows and banks in DRAM (2015) as a story · 1 points
HN discussionSubmitted Observing interrupts from userland on x86 as a story · 1 points
HN discussionSubmitted AssMark received offer to not release rowhammer test as a story · 1 points
HN discussion
