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SEGGER Blog

Company blog · blog.segger.comhardwareprogramming

SEGGER Blog is the company blog at blog.segger.com, writing about hardware and programming. Since 2017, 8 different Hacker News readers have linked it 17 times, most often “Code size: Closing the gap between RISC-V and Arm for embedded applications”. It is still writing: the last post was on 2026-10-21, and you can follow it by feed.

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17mentions?
8HN people?
2017–2025first – last linked?
Links on Hacker News per year · peak 7 in 2021

Too few sampled comments (2) to say how often HN recommends it.?

Why HN links it

HN readers link SEGGER's blog posts on embedded development topics such as RISC-V and ARM code size and floating point emulation, often as technical background or supporting references.

Summarised by Claude from a sample of 2 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.

See what's cooking at SEGGER

Most-linked posts?

  1. Code size: Closing the gap between RISC-V and Arm for embedded applications
    2 people · 2 mentions · first linked 2020-12-02

What Hacker News says?

  1. > with significantly higher code density. This is not correct and is a known weakness of RISC-V at the moment. The ARM toolchains are really good and have decades of improvements in them. This is a big issue for those who need to buy ROM in volume. Better tools are coming online though. For example: https://blog.segger.com/code-size-closing-the-gap-between-ri... "One of the issues faced by RISC-V developers is that…

    Comment linking /code-size-closing-the-gap-between-risc-v-and-arm-for-embedded-applications/

    on “RISC-V is succeeding”
  2. Submitted Smash: An efficient compression algorithm for microcontrollers as a story · 83 points

    HN discussion
  3. An interesting non-free alternative is the SEGGER Runtime Library [1] which works with GCC, but with smaller code size than newlib-nano and significantly faster floating point emulation [2] for processors like the Cortex M3 or RISCV wih no FPU. It would be interesting to see if newlib-nano or picolibc could use these tricks. [1] https://www.segger.com/products/development-tools/runtime-li... [2] https://blog.segger.…

    Comment linking /floating-point-face-off/

    on “Picolibc – Libc for Embedded Systems”
  4. Submitted Algorithms for division: Using Newton's method as a story · 45 points

    HN discussion
  5. Submitted ARM Thumb-2 has a higher code density than RISC-V(RV32IMAC req. ~18% more text) as a story · 3 points

    HN discussion
  6. Submitted Algorithms for division: Using Newton's method as a story · 3 points

    HN discussion
  7. Submitted Reviving a classic electronic game using SEGGER tools and software (Part I) as a story · 2 points

    HN discussion
  8. Submitted Securing embedded systems with digital signatures: The basics as a story · 2 points

    HN discussion
  9. Submitted Saving power in embedded systems – Reducing idle CPU speed as a story · 2 points

    HN discussion
  10. Submitted Correlating and visualizing data sampling, current consumption, and execution as a story · 2 points

    HN discussion
  11. Submitted The SEGGER Linker – Replacing the GNU Linker as a story · 2 points

    HN discussion
  12. Submitted CPU Design at Segger as a story · 1 points

    HN discussion
  13. Submitted Algorithms for Division: Classics as a story · 1 points

    HN discussion
  14. Submitted Working at SEGGER Microcontroller: The question of “why?” as a story · 1 points

    HN discussion
  15. Submitted Segger Embedded Studio on Apple M1 and Intel I7 as a story · 1 points

    HN discussion
  16. Submitted Code Size: Squeezing more with linker outlining as a story · 1 points

    HN discussion
  17. Submitted Code size: Closing the gap between RISC-V and Arm for embedded applications as a story · 1 points

    HN discussion

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