Top all-time · #17241
Sigasi
Company blog · sigasi.com/contenthardwareprogramming
Sigasi is the company blog at sigasi.com, writing about hardware and programming. Since 2011, 4 different Hacker News readers have linked it 5 times. It is still writing: the last post was on 2026-07-24, and you can follow it by feed.
Too few sampled comments (1) to say how often HN recommends it.?
Why HN links it
Linked as a resource on the pitfalls of Verilog for hardware designers, offered alongside MyHDL as a Python-based alternative to Verilog and VHDL. The only comment is a bare pointer, with no judgement of the writing.
Summarised by Claude from a sample of 1 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Sigasi Visual HDL is a purpose-built tool for FPGA and ASIC chip designers to save money and time while increasing the quality of their designs. It lets system architects and hardware engineers create, integrate, validate, and organize HDL. First time right. Sigasi Visual HDL platform (SVH) is devel
What Hacker News says?
MyHDL plug: http://www.myhdl.org/doku.php Don't use Verilog or VHDL, use Python and compile to both while avoiding Verilog's pitfalls! http://www.sigasi.com/content/pitfalls-for-circuit-girls
Comment linking /content/pitfalls-for-circuit-girls
on “How FPGAs work, and why you'll buy one”Submitted VHDL's Crown Jewel as a story · 54 points
HN discussionSubmitted (VHDL editors) Rename: Emacs vs. Sigasi as a story · 2 points
HN discussionSubmitted Be careful with VHDL operator precedence as a story · 1 points
HN discussionSubmitted How VHDL preserves determinism as a story · 1 points
HN discussion