Top all-time · #11943
solidpixel
Personal blog · solidpixel.github.ioprogramminghardware
solidpixel is a personal blog at solidpixel.github.io about programming and hardware. Since 2022, 6 different Hacker News readers have linked it 6 times, most often “An SVE backend for astcenc (Adaptive Scalable Texture Compression Encoder)”. No feed was found, so read it on the site itself.
Too few sampled comments (2) to say how often HN recommends it.?
Why HN links it
HN readers link this post for its critique of fixed-width SIMD instruction sets. Commenters discuss vector widths, variable-length vector ISAs, and how much code must be rewritten for new SIMD extensions.
Summarised by Claude from a sample of 2 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Most-linked posts?
- An SVE backend for astcenc (Adaptive Scalable Texture Compression Encoder)3 people · 3 mentions · first linked 2024-08-06
What Hacker News says?
> Also there are processors with larger vector length How do these fare in terms of absolute performance? The NEC TSUBASA is not a CPU. > Do you have more examples of this? I ported some numeric simulation kernel to the A64Fx some time ago, fixing the vector width gave a 2x improvement. Compilers probably/hopefully have gotten better in the mean time and I haven't redone the experiments since then, but I'd be surpri…
Comment linking /astcenc_meets_sve
on “Fundamental flaws of SIMD ISAs (2021)”Submitted Creating invariant floating-point accumulators as a story · 40 points
HN discussion> we somewhat maxed out at 512 bits Which still means you have to write your code at least thrice, which is two times more than with a variable length SIMD ISA. Also there are processors with larger vector length, e.g. 1024-bit: Andes AX45MPV, SiFive X380, 2048-bit: Akeana 1200, 16384-bit: NEC SX-Aurora, Ara, EPI > no way around this You rarely need to rewrite SIMD code to take advantage of new extensions, unless so…
Comment linking /astcenc_meets_sve
on “Fundamental flaws of SIMD ISAs (2021)”Submitted An SVE backend for astcenc (Adaptive Scalable Texture Compression Encoder) as a story · 9 points
HN discussionSubmitted Vertex Packing as a story · 1 points
HN discussionSubmitted Texture Sampling Tips as a story · 1 points
HN discussion