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xillybus.com
Company blog · xillybus.com/tutorialshardwaresystems
xillybus.com is the company blog at xillybus.com, writing about hardware and systems. Since 2016, 8 different Hacker News readers have linked it 11 times, most often “How PCI express devices talk”. It is still writing: the last post was on 2026-05-19, and you can follow it by feed.
Too few sampled comments (7) to say how often HN recommends it.?
Why HN links it
Xillybus tutorials on PCI Express, covering TLPs and how PCIe interacts with the CPU. Commenters point to them as primers for learning how PCI Express works.
Summarised by Claude from a sample of 7 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Most-linked posts?
- How PCI express devices talk3 people · 3 mentions · first linked 2016-11-28
- /tutorials/pci-express-tlp-pcie-primer-tutorial-guide-22 people · 2 mentions · first linked 2021-06-28
What Hacker News says?
I found this article to be helpful on how PCIe interacts with the CPU: http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tu...
Comment linking /tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1
on “Learning to Read X86 Assembly Language”Submitted How PCI express devices talk as a story · 64 points
HN discussionI am talking about the platform more than the ISA. Some interesting resources: https://sites.google.com/site/pinczakko/system-address-map-i... https://www.youtube.com/playlist?list=PLBTQvUDSl81dTG_5Uk2my... http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tu... http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tu... https://www.amazon.com/Quick-Boot-Pete-Dice/dp/1501515381/ https://opensecuritytrain…
Comment linking /tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2
on “x86 Bare Metal Examples: Minimal operating systems, learn x86 system programming”Submitted Down to the TLP: How PCI Express Devices Talk (Part I) as a story · 3 points
HN discussionHave you tried Vivado? Xilinx ISE is hands down terrible, but supposedly Vivado was "500 man-years of engineering effort" [1]. Unfortunately, vendor lock-in means I can't try Altera's tools for my boards, but Vivado's high level synthesis is really cool. It generates a hardware design from a given C program, and then let's you tune the generated verilog [2]. [1]: http://www.eejournal.com/archives/articles/20120501-b…
Comment linking /tutorials/vivado-hls-c-fpga-howto-1
on “RISC-V Offers Simple, Modular ISA”If you really want to know how PCI Express works I would instead recommend these: http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tu... http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tu...
Comment linking /tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2
on “How PCI-Express works (2020)”Yeah, PCI writes can be posted. It's still very very slow and will end up using an inefficient small transaction size on the PCIe side of things. And posting doesn't help with reads, of course. PCI devices that are cache coherent and can cache snoop and otherwise work with WB cache mode can be written a lot faster. UC writes are something like sequentially consistent (program order reordering with other operations i…
Comment linking /tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1
on “Understanding x86_64 Paging”I love the comic on the right ( http://xillybus.com/media/comic-300px.jpg ). Never heard of this software yet. Amazing that it is part of the Linux kernel (in terms of part of the Ubuntu distribution, for instance).
Comment linking /media/comic-300px.jpg
on “How PCI express devices talk”https://github.com/antmicro/wireshark-pcie-dissector or https://github.com/sora/wireshark-pcie/blob/master/plugins/p... (The PCIe wire format consists of TLPs and DLLPs. Context: https://xillybus.com/tutorials/pci-express-tlp-pcie-primer-t... )
Comment linking /tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2
on “Linux kernel framework for PCIe device emulation, in userspace”
