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blog.stuffedcow.net
Personal blog · blog.stuffedcow.nethardwaresystems
blog.stuffedcow.net is a personal blog at blog.stuffedcow.net about hardware and systems. Since 2012, 30 different Hacker News readers have linked it 43 times, most often “Measuring Reorder Buffer Capacity”. It is still writing: the last post was on 2026-07-08, and you can follow it by feed.
Most-linked posts?
- Measuring Reorder Buffer Capacity6 people · 7 mentions · first linked 2013-07-25
- Windows 9x TLB Invalidation Bug5 people · 7 mentions · first linked 2021-11-27
- Discovering hard disk physical geometry through microbenchmarking (2019)4 people · 5 mentions · first linked 2020-11-08
- Discovering Hard Disk Physical Geometry Through Microbenchmarking3 people · 4 mentions · first linked 2019-10-07
- TLB and Pagewalk Coherence in x86 Processors (2015)3 people · 3 mentions · first linked 2021-01-21
- Store-to-Load Forwarding and Memory Disambiguation in x86 Processors2 people · 3 mentions · first linked 2014-06-15
- Microwave spontaneously turned on by its LED display2 people · 2 mentions · first linked 2024-09-08
- Measuring Reorder Buffer Capacity2 people · 2 mentions · first linked 2025-10-02
What Hacker News says?
Putting together a decent automated test suite is possible, but is a significant project for an individual drive reviewer. And any test suite you create is only good for a few years at most before you have to start worrying about new technologies that change performance or power characteristics in a way your tests can't capture. If you were putting together a hard drive test suite a few years ago to use for reviewin…
Comment linking /2019/09/hard-disk-geometry-microbenchmarking/
on “Western Digital admits 2TB-6TB WD Red NAS drives use shingled magnetic recording”Submitted Microwave spontaneously turned on by its LED display as a story · 168 points
HN discussionHard drives generally use a fairly simple linear mapping between LBAs and physical location. Low LBAs are on the outer edge of the platter where transfer speeds are highest, and high LBAs are on the inner edge where speeds are lowest. Unlike SSDs, hard drives don't need wear leveling, so there's no reason to break from that pattern except in the relatively rare instance of damaged sectors. At smaller scales, the lay…
Comment linking /2019/09/hard-disk-geometry-microbenchmarking/
on “Everything I Know About SSDs”Submitted Discovering Hard Disk Physical Geometry Through Microbenchmarking as a story · 152 points
HN discussionbut rather, you can't let the VM manage its own PTEs. virtualbox lets you configure that - just turn off nested paging The background information for that reason is contained in these two detailed articles: https://blog.stuffedcow.net/2015/08/pagewalk-coherence/ https://blog.stuffedcow.net/2015/08/win9x-tlb-invalidation-b... tl;dr: newer AMD processors have non-coherent pagewalks. Intel has maintained coherent pagew…
Comment linking /2015/08/win9x-tlb-invalidation-bug/
on “VMware mouse driver for Windows 3.x”Submitted Discovering hard disk physical geometry through microbenchmarking (2019) as a story · 83 points
HN discussion> - call/return address mismatch Definitely, it's as important as ever. If you have matched call/ret pairs but cause an address mismatch by say modifying the return value on the stack, the subsequent `ret` will mispredict. OTOH, if you cause a mismatch by having unbalanced call ret pairs, e.g., a `call` to a location that does a `jmp` back instead of a ret, the situation is much worse: the ret prediction stack is mi…
Comment linking /2018/04/ras-microbenchmarks
on “Performance Speed Limits”Submitted TLB and Pagewalk Coherence in X86 Processors as a story · 75 points
HN discussionYou (and a lot of people) make it sound like its magic but it's not - http://blog.stuffedcow.net/2014/01/x86-memory-disambiguation...
Comment linking /2014/01/x86-memory-disambiguation/
on “Introducing SIMD.js”Submitted TLB and Pagewalk Coherence in x86 Processors (2015) as a story · 72 points
HN discussionI see how it worked. That measurement uses the 2013 technique published by Henry Wong. I think it’s probably a reasonable estimate of the instruction window length but to say that’s the same as the buffer size is making a number of architectural assumptions that I haven’t seen any evidence to justify. I suppose in the end it doesn’t really matter as users of the chip though. http://blog.stuffedcow.net/2013/05/measur…
Comment linking /2013/05/measuring-rob-capacity/
on “What do RISC and CISC mean in 2020?”Submitted Microbenchmarking return address branch prediction (2018) as a story · 30 points
HN discussionThese graphs look linear to you? https://blog.stuffedcow.net/2012/07/ivy-bridge-power-consump... https://qph.cf2.quoracdn.net/main-qimg-61820a6b86759c354d41d...
Comment linking /2012/07/ivy-bridge-power-consumption/
on “Apple announces new flagship M2 processor”Submitted Store-to-Load Forwarding and Memory Disambiguation in x86 Processors as a story · 26 points
HN discussionFor those interested in the number of physical registers on a modern CPU, Henry Wong and Travis Downs have done some great work deducing the physical implementation of recent Intel cores: https://travisdowns.github.io/blog/2019/06/11/speed-limits.h... http://blog.stuffedcow.net/2013/05/measuring-rob-capacity/ https://travisdowns.github.io/blog/2019/12/05/kreg-facts.htm... https://travisdowns.github.io/blog/2020/05/2…
Comment linking /2013/05/measuring-rob-capacity/
on “The Intel 8086 processor's registers: from chip to transistors”Submitted Measuring Reorder Buffer Capacity as a story · 4 points
HN discussionI wish the author would have been more specific about the processor being tested. This is the sort of thing that is extremely dependent on the microarchitecture of processor used. I wonder if he's testing on AMD or older Intel? Modern Intel chips usually do an very good job of "store-to-load forwarding" when the load is the same size or smaller than the store. Although it's testing a slightly different effect, this…
Comment linking /2014/01/x86-memory-disambiguation/
on “Counting bytes fast”Submitted TLB and Pagewalk Coherence in x86 Processors (2015) as a story · 3 points
HN discussionOn the other hand, having no cached result for the branch probably correlates strongly with not having the target in I-cache, which means you may be stalling out anyway. It also implies that the branch is not in the middle of a tight loop. Regarding the size of the ROB, I was wondering about the size a while ago and found an interesting post from someone who measured it for modern Intel processors: Ivy Bridge (168),…
Comment linking /2013/05/measuring-rob-capacity/
on “The cost of dynamic vs. static dispatch in C++”Submitted Windows 9x TLB Invalidation Bug as a story · 3 points
HN discussionAMD has relaxed a bit coherency behavior after page table manipulation leading to Windows 9x crashes: https://blog.stuffedcow.net/2015/08/win9x-tlb-invalidation-b... These crashes are not related to clock speed. While Windows 9x already cannot run on these CPU due to clock speed, the clock speed issues have mostly been patched in 9x.
Comment linking /2015/08/win9x-tlb-invalidation-bug/
on “86Box: Why Not Pentium III?”Submitted Discovering Hard Disk Physical Geometry through Microbenchmarking as a story · 3 points
HN discussionRunning or virtualizing DOS-era software can be non-trivial: see, for example, Windows 98 vs TLB cache invalidation behavior in modern CPUs https://blog.stuffedcow.net/2015/08/win9x-tlb-invalidation-b... requiring a patch. Any code that does loop counting to estimate cycles for sleep() will also overflow (hello, Pascal CRT Error 200!) requiring a different patch.
Comment linking /2015/08/win9x-tlb-invalidation-bug/
on “Intel: New Core Ultra Processors Deliver Breakthrough Performance”Submitted TLB and Pagewalk Coherence in X86 Processors as a story · 3 points
HN discussionThe specifics of how data is physically arranged across multiple platters is undocumented, complicated, and varies between models. But with some clever benchmarks, much of that information can be inferred: https://blog.stuffedcow.net/2019/09/hard-disk-geometry-micro... A hard drive will only use one head on one platter at a time. A single logical block will be contained within a single track on one platter. The next…
Comment linking /2019/09/hard-disk-geometry-microbenchmarking/
on “HDD Components Maker Hoya Describes 22TB and 24TB Hard Drives”Submitted Measuring CPU instruction reorder buffer capacity. (2013) as a story · 2 points
HN discussionVery cool. Other similar and interesting non-LRU caches: MySQL https://medium.com/@arpitbhayani/what-makes-mysql-lru-cache-... Intel Sandy Bridge+ https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/
Comment linking /2013/01/ivb-cache-replacement/
on “DragonFlydb: Cache Design”Submitted Measuring performance benefits of hyper-threading as a story · 2 points
HN discussionI think it does not matter, skipping means the CPU does not execute it, but it still has room in RoB which is enough for defending Spectre. see this article: http://blog.stuffedcow.net/2013/05/measuring-rob-capacity/
Comment linking /2013/05/measuring-rob-capacity/
on “Oo7: Low-Overhead Defense Against Spectre Attacks”Submitted Discovering Hard Disk Physical Geometry Through Microbenchmarking (2019) as a story · 1 points
HN discussion
