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Codasip
Company blog · codasip.comhardwaresecurity
Codasip is the company blog at codasip.com, writing about hardware and security. Since 2017, 15 different Hacker News readers have linked it 17 times, most often “Does ISA Ownership Matter? A Tale of Three ISAs”. It is still writing: the last post was on 2026-10-20, and you can follow it by feed.
Too few sampled comments (7) to say how often HN recommends it.?
Why HN links it
HN commenters cite Codasip's articles and product pages on RISC-V, CHERI, ISA ownership and licensing costs, mostly as sources for their own points about processor cores.
Summarised by Claude from a sample of 7 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Codasip is redefining secure silicon, building the foundation of the next era of secure computing. Codasip - Resilient by Design.
Most-linked posts?
- Does ISA Ownership Matter? A Tale of Three ISAs2 people · 2 mentions · first linked 2020-12-23
- The first commercial implementation of CHERI technology2 people · 2 mentions · first linked 2024-02-25
- Fine-grained memory protection with the first commercial implementation of CHERI2 people · 2 mentions · first linked 2023-11-11
What Hacker News says?
I suspect it's due to fundamentally different ownership forces acting on the ISAs. ARM may be a good choice now, but it's recently been put into the hands of someone who has a stake in the market which buys ARM licenses (Nvidia), and became non-neutral. ISAs change, and there was a recent article written about this particular situation too: https://codasip.com/2020/12/22/does-isa-ownership-matter-a-t...
Comment linking /2020/12/22/does-isa-ownership-matter-a-tale-of-three-isas/
on “Ask HN: What Lived Up to the Hype?”Submitted Does ISA Ownership Matter? A Tale of Three ISAs as a story · 39 points
HN discussionThe place you can get a real physical commercially available CHERI implementation is RISC-V: https://codasip.com/press-release/2023/10/31/codasip-deliver... That's largely because if you base a product on Arm or MIPS you have the choice of getting them to actively invest in and support you, or getting sued into oblivion by them. THAT is why RISC-V is the most friendly ISA to innovation and where most future innovati…
Comment linking /press-release/2023/10/31/codasip-delivers-processor-security-to-actively-prevent-cyberattacks/
on “How to improve the RISC-V specification”Submitted Five Good Things About RISC-V as a story · 18 points
HN discussionSome information I found at https://codasip.com/swerv : The SweRV Core™ EH1 is an advanced high-performance core with small footprint, suitable for embedded devices supporting data-intensive applications such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. SweRV Core EH1: Architecture: 32-bit, dual superscalar, 9-stage pipeline Performance: Up to 4.95 Cor…
Comment linking /swerv
on “Western Digital SweRV RISC-V Core”Submitted The first commercial implementation of CHERI technology as a story · 4 points
HN discussionWhatever the 1.5% ARM royalty fee is for your org: https://www.codasip.com/2017/04/11/risc-vs-impact-on-process... For someone like Western Digital, that's probably a huge deal. I don't think it saves the RPi folks much. I suspect they get a loss leader deal. The total volume can't be that high, but it's good press for Texas Instruments.
Comment linking /2017/04/11/risc-vs-impact-on-processor-ip-licensing-fees/
on “Raspberry Pi Foundation Announces RISC-V Foundation Membership”Submitted Codasip board initiates an expedited process to sell the company as a story · 3 points
HN discussionCHERI-RISC-V is being standardised [1], Codasip is working on a commercial implementation of CHERI-RISC-V [2], and lowRISC is working on the Sonata project [3] implementing CHERIoT. The Early performance results from the prototype Morello microarchitecture report [4] predicts the overhead between 1.8% and 3.0%. We don’t know what that overhead would be in production until such a commercial implementation is delivere…
Comment linking /solutions/riscv-processor-safety-security/cheri/
on “C can be memory safe”Submitted Codasip announces strategic pivot and divestiture as a story · 2 points
HN discussionThat is not true. Two days ago lowRISC announced that OpenTitan used in Google Chromebooks will include CHERI: https://lowrisc.org/news/opentitan-earl-grey-2-to-support-ch... Last year, Google announced that their Coral NPU will include CHERI: https://developers.googleblog.com/en/introducing-coral-npu-a... There are more cores that companies are actively working on: X730 from Codasip https://codasip.com/solutions/ri…
Comment linking /solutions/riscv-processor-safety-security/cheri/x730-risc-v-application-processor/
on “RISC-V Is Inevitable: State of the Union Keynote Argues”Submitted Dongwoon Anatech Licenses Codasip’s Bk3 RISC-V Processor as a story · 2 points
HN discussionAnother risc-v: https://www.codasip.com/2018/01/10/codasip-processors-not-af...
Comment linking /2018/01/10/codasip-processors-not-affected-by-meltdown-and-spectre/
on “SiFive’s RISC-V Core IP Offerings Are Not Affected by Meltdown and Spectre”Submitted Bk5-64, a New 64-bit RISC-V Processor as a story · 2 points
HN discussionSubmitted Fine-grained memory protection with the first commercial implementation of CHERI as a story · 1 points
HN discussionSubmitted Codasip delivers processor security to actively prevent most common cyberattacks as a story · 1 points
HN discussionSubmitted Buffer Bound Vulnerabilities and Their Dangers as a story · 1 points
HN discussion
