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Georg's Log
Personal blog · gms.tfsystemsprogrammingsecurity
Georg's Log is a personal blog at gms.tf about systems, programming and security. Since 2018, 16 different Hacker News readers have linked it 26 times, most often “Programming with RISC-V Vector Instructions”. It is still writing: the last post was on 2026-10-19, and you can follow it by feed.
Too few sampled comments (7) to say how often HN recommends it.?
Why HN links it
HN readers link Georg's Log for its RISC-V vector extension article, cited to explain vector-length-agnostic code, and for a post on syscall costs. Comments cite these posts without judging them.
Summarised by Claude from a sample of 7 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Most-linked posts?
- Programming with RISC-V Vector Instructions6 people · 7 mentions · first linked 2020-08-06
- On the Costs of Syscalls (2021)4 people · 4 mentions · first linked 2021-09-01
- The Rise of Meson2 people · 4 mentions · first linked 2021-08-09
What Hacker News says?
Where is the state/registers written to then if not L1? I'm confused. What do you say about the measurements from https://gms.tf/on-the-costs-of-syscalls.html ? Table suggests that the cost is by a magnitude larger, depending on the CPU host, from 250 to 620ns.
Comment linking /on-the-costs-of-syscalls.html
on “Fast UDP I/O for Firefox in Rust”Submitted Programming with RISC-V Vector Instructions as a story · 162 points
HN discussion> That doesn't make sense --- how would the code know how much to increment pointers by, how many times to loop, alignment, etc. ? You ask the hardware. The current vector width is a register that can be set and queried. https://gms.tf/riscv-vector.html
Comment linking /riscv-vector.html
on “PicoRio Linux RISC-V SBC is an open-source alternative to Raspberry Pi board”Submitted On the Costs of Syscalls (2021) as a story · 105 points
HN discussionRISC-V has a solution to this which seems quite elegant - the vector length is set by the program, up to some maximum, and for the final block, it is simply whatever is left: https://gms.tf/riscv-vector.html
Comment linking /riscv-vector.html
on “Speeding up atan2f”Submitted The Rise of Meson as a story · 74 points
HN discussionRISC-V is also adding Vector extensions. The cool thing about those is that they are variable length, so code can take advantage of newer hardware / degrade gracefully on less capable one. https://gms.tf/riscv-vector.html
Comment linking /riscv-vector.html
on “What's wrong with Intel, and how to fix it: Former principal engineer unloads”Submitted Injecting Code into a Linux Process as a story · 6 points
HN discussionThanks, this is super helpful. I didn't know about that feature of the SVE instructions. I was curious and it looks like RISC-V takes it a step further even and is "Vector Length Agnostic"[1]. Pretty cool! [1]: https://gms.tf/riscv-vector.html
Comment linking /riscv-vector.html
on “Show HN: Up to 100x Faster FastAPI with simdjson and io_uring on Linux 5.19”Submitted Scanning I2C Addresses as a story · 5 points
HN discussionI checked https://NN-512.com and gituhb, trying to grok. reading: https://gms.tf/riscv-vector.html VLA (vector length agnostic) indirection makes the execution harder to control? So... RISC-V does not provide instructions for each exponent MMX(64), SSE(128), AVX(256), AVX512(512) and therefore the the compiler/assembler/human needs to use the input-length-agnostic instructions which the hardware lowers to operations…
Comment linking /riscv-vector.html
on “Intel joins RISC-V international and invests another billion in foundry”Submitted Blocking Audio Ads as a story · 4 points
HN discussionThis looks like a curious case, non-fixed-length vectorization code in RISC-V: > "Perhaps the most interesting part of the open RISC-V instruction set architecture (ISA) is the vector extension (RISC-V "V"). In contrast to the average single-instruction multipe-data (SIMD) instruction set, RISC-V vector instructions are vector length agnostic (VLA). Thus, a RISC-V "V" CPU is flexible in choosing a vector register si…
Comment linking /riscv-vector.html
on “Vectorization: Introduction”Submitted Getting started with the GD32VF103 RISC-V Microcontroller as a story · 4 points
HN discussionSubmitted Better Datamash Build Story with Meson as a story · 2 points
HN discussionSubmitted The Rise of Meson (2021) as a story · 2 points
HN discussionSubmitted On the Costs of Syscalls as a story · 2 points
HN discussionSubmitted The Rise of Meson as a story · 2 points
HN discussionSubmitted Dtracing Passwords for Fun as a story · 2 points
HN discussionSubmitted The Rise of Meson as a story · 1 points
HN discussionSubmitted The curious case of nanosleep vs. HR_sleep as a story · 1 points
HN discussionSubmitted Shift Typing as a story · 1 points
HN discussionSubmitted On the Costs of Syscalls as a story · 1 points
HN discussionSubmitted On Sprintf() Fails (2016) as a story · 1 points
HN discussionSubmitted Deploying full disk encryption in the cloud as a story · 1 points
HN discussionSubmitted Std: Find() and Memchr() Optimizations (2016) as a story · 1 points
HN discussion
